Integrated circuits are currently fabricated in a series of process steps whereby a given layer is formed, patterned, and modified, and then subsequent layers are formed on top of the given layer until the fabrication of the integrated circuit is complete. For example, a layer of an electrically insulating material may be formed over the top of a layer of an electrically conducting material, and then patterned to define areas where openings will be formed in the electrically insulating layer, and then modified to create the openings through the electrically insulating layer and down to the electrically conducting layer. This iterative process of forming, patterning, and modifying a layer is repeated many times during the fabrication of an integrated circuit. Of course, there are many extremely complex modifications to and variations of this very basic description as presented, but this description is sufficient to introduce the concepts that are described in association with the invention disclosed and claimed herein.
As a part of the process whereby the layer is patterned, a layer of a photosensitive material, or photoresist, is applied to the surface of the layer in a process such as spin coating. The photoresist is soft baked to remove some of the more volatile components and form a film that has sufficient structural properties for the subsequent use of the film. The photoresist is then exposed to a pattern that is created by passing a light through a mask of some type, in which the pattern has been previously formed. The photoresist is then hard baked to further drive out the volatile components, and the layer underlying the patterned photoresist film is then modified, such as in an etching process.
The mask that is used in the exposure process may have any one of several different forms. For example, the mask may be large enough to cover in a single exposure the entire surface of the substrate on which the integrated circuits are to be formed. In this case, the mask has approximately the same number of integrated circuits within its pattern as are ultimately formed on the substrate.
However, as substrate sizes have increased, this configuration has become less favored. Typically, the mask has fewer device patterns on it than will ultimately be formed on the surface of the substrate, and the images on the mask are stepped across the surface of the substrate in a series of multiple exposures onto subsections of the substrate, until the entire surface of the substrate has been exposed to the images on the mask. For example, the mask may have a block of nine integrated circuit images on it, which are stepped across the surface of the substrate. Masks with properties such as those described herein are typically referred to as reticles.
Typically, just the images for a single mask layer are contained on a single reticle. Thus, if an integrated circuit requires nine different layers, nine different reticles are required for the fabrication of the integrated circuit, and if the integrated circuit requires eighteen different layers, then eighteen different reticles are required for the fabrication of the integrated circuit. As the cost of constructing a reticle has increased dramatically, there has been incentive to find ways to reduce the number of reticles required to fabricate a given integrated circuit pattern.
One method that has been used is to put more than one mask layer on a single reticle. For example, for a reticle with a block of nine images on it, instead of making each of the images in the block of nine the same image, some of the images can be for different mask layers. For example, the top row of three images may be for a first masking layer, the second row of three images may be for a second masking layer, and the third row of three images may be for a third masking layer. As a further example, the nine images may be for nine different masking layers. In this example, if the integrated circuit has only nine masking layers, then only a single reticle is required, and if the integrated circuit has eighteen masking layers, then only two different reticles are required.
In this manner, the number of reticles required to pattern an integrated circuit design is dramatically reduced. However, there are certain other issues that are created with this solution. For example, the throughput of the exposure process tends to be reduced in direct proportion to the decrease in the number of redundant images for a single masking layer on a reticle. In other words, a reticle that contains nine images for a single masking layer has nine times the throughput of a reticle that contains only one image for a single masking layer.
Another issue that is created has to do with the physical properties of the plate on which the patterned images of the reticle are formed, and the physical properties of the lenses and other optics used to transmit the light through the reticle and to the surface of the substrate on which the integrated circuits are to be formed. Because both the plate and the optics tend to have some degree of non-uniformity in their physical properties, an image that formed from one part of the reticle and optics may not be exactly the same as an image that is formed from another part of the reticle and optics.
When a reticle contains a set of only one image, and the set is stepped across the surface of the substrate in a uniform manner from masking layer to masking layer, then individual integrated circuits on the substrate are patterned from images that all originate in the same part of each reticle, and with light that is transmitted through the same part of the optics. Thus, these non-uniformities in physical characteristics tend to not be such a problem in this case.
However, when a reticle has different images within its image set, then a single integrated circuit is formed with images that are originated in different portions of the reticle and through different portions of the optics. These differences in physical characteristics from one position to another may be large enough to create misalignment and other problems between the different layers of the integrated circuit so formed. This problem is called reticle overlay error.
What is needed, therefore, is a system for characterizing and correcting reticle overlay errors.